Shailja Thakur

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New activity in shailja/fine-tuned-codegen-16B-Verilog over 2 years ago

Hardware requirement for inference

2

#1 opened almost 3 years ago by

ronghash

New activity in shailja/fine-tuned-codegen-2B-Verilog almost 3 years ago

what's the purpose of the model? Is it to help generate verilog design?

3

#1 opened almost 3 years ago by

StevenGon

New activity in shailja/Verilog_GitHub almost 3 years ago

🚩 Report : Legal issue(s)

3

#1 opened almost 3 years ago by

zhanghongce

New activity in bigcode/starcoder about 3 years ago

Unable to load model, error

6

#17 opened about 3 years ago by

shailja

Unable to load model, error

6

#17 opened about 3 years ago by

shailja

Unable to load model, error

6

#17 opened about 3 years ago by

shailja